摘要在verilog的编写中可能存在很多的wire和reg需要去声明。gvim中的verilog-mode插件对于写的组合或者时序逻辑这部分的支持貌似并不好。可以使用gvim的快捷键做辅助对这部分进行快捷声明。步骤1在.vimrc中复制如下代码并source Verilog declare: append aligned jump Assumption: one signal per line(wire/reg/input/output xxx;) Keys: leaderdw : declare wire under /*AUTOWIRE*/ leaderdr : declare reg under/*AUTOREG*/ leaderdi : declare input under /*autoinput*/ leaderdo: declare output under/*autooutput*/if!exists(g:verilog_decl_name_col)let g:verilog_decl_name_col 13 Signal name start column (1-based) endif if !exists(g:verilog_decl_indent) let g:verilog_decl_indent indent string: or\tendiffunction!s:FindMarker(marker)abortreturnsearch(\c\/\*\s*.a:marker.\s*\*\/,nw)endfunctionfunction!s:AlreadyDeclared(name)abort 全局上下搜索支持 wire/reg/input/output let pat ^\s*\%(wire\|reg\|input\|output\)\\s*\%(\[[^]]\\]\s*\)\?\ . escape(a:name, \) . \\s*; return search(pat, n) 0 || search(pat, bn) 0 endfunction function! s:PadToNameCol(keyword) abort let name_col get(g:, verilog_decl_name_col, 13) let prefix g:verilog_decl_indent . a:keyword . let spaces name_col - strlen(prefix) return repeat( , spaces 1 ? 1 : spaces) endfunction function! s:IsOnePerLineDecl(kind, line) abort return a:line ~# ^\s* . a:kind . \\s*\%(\[[^]]\\]\s*\)\?\h\w*\s*;\s*$ endfunction function! s:FindInsertAfterDeclBlock(anchor, kind) abort let lnum a:anchor 1 let last a:anchor while lnum line($) let txt getline(lnum) if SIDIsOnePerLineDecl(a:kind, txt) let last lnum let lnum 1 continue endif break endwhile return last endfunction function! s:Declare(marker, kind) abort let name expand(cword) if empty(name) echoerr No identifier under cursor return endif if SIDAlreadyDeclared(name) echom Already declared: . name return endif let anchor SIDFindMarker(a:marker) if anchor 0 echoerr Marker not found:/* . a:marker . */(case-insensitive) return endif let prefix g:verilog_decl_indent . a:kind let newline prefix . SIDPadToNameCol(a:kind) . name . ; let insert_after SIDFindInsertAfterDeclBlock(anchor, a:kind) call append(insert_after, newline) 光标跳到新行定位到信号名 let target_lnum insert_after1 call cursor(target_lnum,1)let name_start strlen(prefix.SIDPadToNameCol(a:kind))1 call cursor(target_lnum,name_start)endfunction nnoremap leaderdw :call SIDDeclare(autowire,wire)CR nnoremap leaderdr :call SIDDeclare(autoreg,reg)CR nnoremap leaderdi :call SIDDeclare(autoinput,input)CR nnoremap leaderdo:call SIDDeclare(autooutput,output)CR 可选一键插入标记映射 nnoremap leadermw :call append(line(.)1,/*AUTOWIRE*/)CR nnoremap leadermr :call append(line(.)1,/*AUTOREG*/)CR nnoremap leadermi:call append(line(.)1,/*autoinput*/)CR nnoremap leadermo :call append(line(.)1,/*autooutput*/)CR需要在verilog的.v文件中存在/*autowire*/和/*autoreg*/。module top ( input clk, input rst_n, input a, input b ); /*autowire*/ /*autoreg*/ always (*) begin comb_sum a ^ b; end always (posedge clk or negedge rst_n) begin if (!rst_n) q 1b0; else q comb_sum; end endmodule在要声明的wire信号光标出按下\dw,在要声明的reg信号光标处按下\dr。/*autowire*/ wire comb_sum; /*autoreg*/ reg q;效果如上。缺点在产生的声明中不会有位宽的识别每次产生声明后光标会自动跳转到声明行可以手动补齐位宽。
