verilog HDLBits刷题“Vector100r”---Combinationl for-loop:Vector reversal 2

一、题目Given a 100-bit input vector [99:0], reverse its bit ordering.Module Declarationmodule top_module( input [99:0] in, output [99:0] out );二、分析可以使用for或generate for循环语句通过i将最低位的输入赋值给最高位输出高低顺序和为99三、代码实现module top_module( input [99:0] in, output [99:0] out ); integer i; always(*) for(i0;i100;ii1)begin out[i]in[99-i]; end endmodulemodule top_module( input [99:0] in, output [99:0] out ); genvar i; generate for(i0;i100;ii1) begin:vector100 assign out[i]in[99-i]; end endgenerate endmodule 或者 module top_module( input [99:0] in, output [99:0] out ); generate genvar i; for(i0;i99;i)begin:my_block assign out[i]in[99-i]; end endgenerate endmodule 或者 module top_module( input [99:0] in, output [99:0] out ); always(*)begin for(int i0;i100;i) out[i]in[100-i-1]; end endmodule