verilog HDLBits刷题[Finite State Machines]“Fsm3”---Simple FSM 3 （asynchronous reset）

1、题目See also: State transition logic for this FSMThe following is the state transition table for a Moore state machine with one input, one output, and four states. Implement this state machine. Include an asynchronous reset that resets the FSM to state A.StateNext stateOutputin0in1AAB0BCB0CAD0DCB12、分析使用one-hot state encoding: A4b0001, B4b0010, C4b0100, D4b1000.还是有点困惑parameter A0, B1, C2, D3;A,B,C,Dbit 下标state[A]→state[0]state[B]→state[1]state[C]→state[2]state[D]→state[3]独热编码规则在状态 Astate 4b0001→state[0]1在状态 Bstate 4b0010→state[1]1在状态 Cstate 4b0100→state[2]1在状态 Dstate 4b1000→state[3]13、代码module top_module( input clk, input in, input areset, output out); // reg [3:0] state,next_state; parameter A0, B1, C2, D3; // State transition logic: Derive an equation for each state flip-flop. assign next_state[A] state[0](~in) | state[2](~in); assign next_state[B] state[0](in) | state[1](in)|state[3](in); assign next_state[C] state[1](~in) | state[3](~in); assign next_state[D] state[2](in); always (posedge clk ,posedge areset)begin if(areset) state4d1; else statenext_state; end // Output logic: assign out (state[D]1b1); endmodule4、结果