verilog HDLBits刷题[Finite State Machines]“Fsm onehot”---One-hot FSM

1、题目Given the following state machine with 1 input and 2 outputs:Suppose this state machine uses one-hot encoding, where state[0] through state[9] correspond to the states S0 though S9, respectively. The outputs are zero unless otherwise specified.Implement thestate transition logicandoutput logicportions of the state machine (but not the state flip-flops). You are given the current state in state[9:0] and must produce next_state[9:0] and the two outputs. Derive the logic equations by inspection assuming a one-hot encoding. (The testbench will test with non-one hot inputs to make sure youre not trying to do something more complicated).2、分析独热编码只有1bit为1其它全为0。有S0-S9一共10个状态但输入已经有当前状态不需要自定义状态。除了图中标注的特定输出其它输出都为0.3、代码module top_module( input in, input [9:0] state, output [9:0] next_state, // wire不要reg output out1, output out2); assign next_state[0] (state[0]~in) | (state[1]~in) | (state[2]~in) | (state[3]~in) | (state[4]~in) | (state[7]~in) | (state[8]~in) | (state[9]~in); assign next_state[1] (state[0]in) | (state[8]in) | (state[9]in); assign next_state[2] (state[1]in); assign next_state[3] (state[2]in); assign next_state[4] (state[3]in); assign next_state[5] (state[4]in); assign next_state[6] (state[5]in); assign next_state[7] (state[6]in) | (state[7]in); assign next_state[8] (state[5]~in); assign next_state[9] (state[6]~in); assign out1 state[8] || state[9]; assign out2 state[7] || state[9]; endmodule 或者 module top_module( input in, input [9:0] state, output reg [9:0] next_state, output out1, output out2); always (*) begin next_state 10d0; // 初始全部清零避免锁存 if(state[0]) begin next_state[0] ~in; next_state[1] in; end if(state[1]) begin next_state[0] ~in; next_state[2] in; end if(state[2]) begin next_state[0] ~in; next_state[3] in; end if(state[3]) begin next_state[0] ~in; next_state[4] in; end if(state[4]) begin next_state[0] ~in; next_state[5] in; end if(state[5]) begin next_state[8] ~in; next_state[6] in; end if(state[6]) begin next_state[9] ~in; next_state[7] in; end if(state[7]) begin next_state[0] ~in; next_state[7] in; end if(state[8]) begin next_state[0] ~in; next_state[1] in; end if(state[9]) begin next_state[0] ~in; next_state[1] in; end end assign out1 state[8] || state[9]; assign out2 state[7] || state[9]; endmodule4、结果